The contributors of research work and publication details are given below.

PhD Students (Awarded):

1. Dr. Divyesh Sachan, Low Power RF Circuits

2. Dr. Jitendra Kumar Mishra, Memory Design

3. Dr. Ankita Verma, Performance of CMOS Receiver

4. Dr. Pritesh Kumar Yadav, Performance of CMOS Receiver

5. Dr. Sandeep Tripathi, Memory Design

6. Dr. Pratiksha Shukla, Low Power Nonvolatile Circuits and Systems

7. Dr. Dipti, Analog to Digital Converter

PhD Students (Ongoing):

1. Ms. Priyanka Tiwari (Non Volatile Memory)

2. Ms. Apsana Khatoon  (Digitally Tunable CMOS Receiver) 

3. Dr. Anurag Pandey, Analog to Digital Converter

4. Mr. Sateesh Kourav (Ultra Wideband Transmitter)

5. Ms. Sandhya Kannaujiya (Ultra Wideband Receiver)

6. Ms. Priyanka Chaurasia (Ultra Wideband Receiver)

7. Mr. Ram Krishna Sharma (Ultra Wideband Transmitter)

Patents:

Prasanna Kumar Misra, Apsana Khatoon and Priyanka Tiwari, "Digitally Programmable Variable Gain Amplifier Using MOSFETs and MTJs for Receiver Systems and Method Thereof" 2026 (Granted).

Prasanna Kumar Misra, Manish Goswami, Priyanka Chaurasia and Ankita Tiwari, "A System and Method for Ultra-Wideband Low Noise Amplification Using a Cross-Coupled Negative Impedance Circuit", 2026 (Filed).

Selected Publications:

[1] S. Tripathi, P. K. Yadav, S. Choudhary, and P. K. Misra, “Power Analysis Attack Resilient Novel 9T & 10T NVSRAM for Emerging Memory,” IEEE Magnetics Letters, 2026.

[2] P. K. Yadav and P. K. Misra, “A 28-GHz mmWave Receiver Frontend With an Improved FOM of 15.56-dB for 5G New Radio in 130-nm BiCMOS Technology,” IEEE Access, vol. 14, pp. 21200–21212, 2026.

[3] Ravi S Siddanath, Mohit Gupta, Deepak Joshi, Souvik Kumar Das, Prasanna Kumar Misra, Manish Goswami, Kavindra Kandpal, "High-Precision Hybrid CMOS/MTJ BGR With Improved Temperature Coefficient and Reduced Area," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2026.

[4] Anurag Pandey, Garima Singh, Dipti, Kavindra Kandpal, Prasanna Kumar Misra, Manish Goswami, "Machine Learning Based Performance Enhancement Design of 16-bit Hybrid Flash-Binary Search ADC with Comparator Reuse Technique" Journal of Circuits, Systems and Computers 2026.

[5] Anurag Pandey, Kashi Bandla, Dipankar Pal, Dipti, Kavindra Kandpal, Prasanna Kumar Misra, Manish Goswami, “Performance improvement in asynchronous binary search ADC using bootstrapped sample and hold circuit & 2-stage ladder network” Analog Integrated Circuits and Signal Processing 2025, Vol. 124, No.1, pp. 1-24.

[6] S. Tripathi, S. Choudhary, and P. K. Misra, “An 8T PA Attack Resilient NVSRAM for In-Memory-Computing Applications,” IEEE Transactions on Circuits and Systems-I: Regular Papers, 2023.

[7] S. Tripathi, S. Choudhary, and P. K. Misra, “Highly Reliable, Stable and Store Energy Efficient 8T/9T-2D-2MTJ NVSRAMs,” IEEE Transactions on Nanotechnology, 2023.

[8] P. Shukla, P. Kumar, and P. K. Misra, “An Energy Efficient, Mismatch Tolerant Offset Compensating Hybrid MTJ/CMOS Magnetic Full Adder,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2022.

[9] S. Tripathi, S. Choudhary, and P. K. Misra, “A Novel STT-SOT MTJ Based Nonvolatile SRAM for Power Gating Applications,” IEEE Transactions on Electron Devices, 2022.

[10] P. Shukla, P. Kumar, and P. K. Misra, “A Highly Reliable Dynamic Logic Based Hybrid MTJ/CMOS Magnetic Full Adder for High Performance and Low Power Application,” IEEE Transactions on Magnetics, 2022.

[11] Dipti, Sajai Vir Singh, Tushar Kumawat, Anush Bekal, Prasanna Kumar Misra, Manish Goswami, “A 13.8 pJ/conv-step binary search ADC with reusable comparator architecture”, AEU-International Journal of Electronics and Communications, Vol 144, 2022.

[12] A. Verma, P. K. Yadav, M. Goswami, and P. K. Misra, “A Differential LNA Architecture with Improved Figure of Merit Using 40 nm UMC CMOS Technology for mmWave Band Receiver Applications,” Wireless Personal Communications, vol. 124, pp. 783–799, 2022.

[13] P. K. Yadav, A. Verma, and P. K. Misra, “A Proposed Technique to Improve the Performance of Receiver by Using Linear Gm-C Low Pass Filter for mmWave Band Applications,” Journal of Circuits, Systems, and Computers, June 2021.

[14] P. K. Yadav and P. K. Misra, “Tunable Bandpass Filter using Double Resistive Feedback Floating Active Inductor for 5GHz Wireless LAN Applications,” Analog Integrated Circuits and Signal Processing, May 2021.

[15] D. Sachan, M. Goswami, and P. K. Misra, “Design of Ultra-Low Power High-Q Single Ended Active Inductors for IF BPF of Receiver Frontend using 130nm BiCMOS Technology,” Wireless Personal Communications, April 2021.

[16] A. Verma, P. K. Yadav, S. Ambulker, M. Goswami, and P. K. Misra, “A 36.7 mW, 28 GHz Receiver Frontend using 40nm RFCMOS Technology with Improved Figure of Merit,” Analog Integrated Circuits and Signal Processing, Jan. 2021.

[17] J. K. Mishra, L. L. Mankali, K. Kandpal, P. K. Misra, and M. Goswami, “Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High Speed Applications,” Journal of Circuits, Systems and Computers, vol. 30, issue 15, 2021.

[18] Dipti, Sanjai Vir Singh, Rohit Joshi, Prasanna Kumar Misra and Manish Goswami, "A reusable stage based reduced comparator count binary search ADC,” Analog Integrated Circuits and Signal Processing , July 2020.

[19] J. K. Mishra, B. B. Upadhyay, P. K. Misra, and M. Goswami, “Design and Analysis of SRAM Cell using Body Bias Controller for Low Power Applications,” Circuits, Systems, and Signal Processing, Nov. 2020.

[20] J. K. Mishra, H. Srivastava, P. K. Misra, and M. Goswami, “Analytical Modelling and Design of 9T SRAM Cell with Leakage Control Technique,” Analog Integrated Circuits and Signal Processing, pp. 1–13, 2019.

[21] D. Sachan, M. Goswami, and P. K. Misra, “A High-Q Floating Active Inductor using 130nm BiCMOS Technology and Its Application in IF Band Pass Filter,” Analog Integrated Circuits and Signal Processing, pp. 1–9, 2018.

[22] D. Sachan, H. Kumar, M. Goswami, and P. K. Misra, “A 2.4 GHz Low Power Low Phase-Noise Enhanced FOM VCO for RF Applications using 180nm CMOS Technology,” Wireless Personal Communications, vol. 101, issue 1, pp. 391–403, 2018.

[23] P. K. Misra and S. Qureshi, “A Technique to Improve the Performance of NPN HBT on Thin Film SOI,” IEEE Journal of the Electron Devices Society, vol. 1, no. 4, pp. 92–98, Apr. 2013.

Conference Publications:

[1] A. Shrivastava, S. V. Nirmal, P. K. Misra, and P. K. Yadav, “A 2.4 GHz Down-Conversion Mixer with Improved Figure of Merit for WLAN Applications,” in 2025 IEEE 9th International Conference on Information and Communication Technology, 2025.

[2] R. S. Siddanath, A. Maurya, M. Gupta, P. K. Misra, M. Goswami, and K. Kandpal, “FinFET-Based Fast-Recovering Radiation-Hardened 14T (FRRH14T) SRAM for Space Applications,” in 2025 IEEE 22nd India Council International Conference (INDICON), pp. 1–6, 2025.

[3] P. Chaurasia, A. Verma, M. Goswami, and P. K. Misra, “A Proposed Ultra Wide Band Low Noise Amplifier with Improved Gain Using Negative Impedance Circuit,” in 2025 IEEE 22nd India Council International Conference (INDICON), pp. 1–5, 2025.

[4] S. Kannaujiya, P. Tiwari, K. Kandpal, and P. K. Misra, “Digitally Programmable FinFET/MTJ Voltage Controlled Oscillator for UWB Receiver,” in 2025 IEEE Microwaves, Antennas, and Propagation Conference (MAPCON), pp. 1–4, 2025.

[5] S. Kourav, P. K. Yadav, M. Goswami, and P. K. Misra, “A Dual-Band Low-Noise Amplifier for 20 GHz 6G Communication and 77 GHz Radar Sensing,” in 2025 IEEE Microwaves, Antennas, and Propagation Conference (MAPCON), pp. 1–4, 2025.

[6] P. K. Yadav, S. Ambulker, and P. K. Misra, “A FinFET-based Active Inductor for UWB Applications for 1.0–9.3 GHz Frequency,” in 2025 IEEE 7th International Conference on Emerging Electronics (ICEE), pp. 1–4, 2025.

[7] R. Kanojia and P. K. Misra, “A 35 mW, 2.4 dB Noise Figure, 28 GHz Low-IF CMOS Receiver Front-end with 1 GHz Bandwidth,” in 2025 IEEE 7th International Conference on Emerging Electronics (ICEE), pp. 1–4, 2025.

[8] P. Tiwari, A. Khatoon, and P. K. Misra, “An 18 nm FinFET with STT-PMA MTJs: A Hybrid Memory Cell Architecture for Energy-Efficient Analog In-Memory Computing,” in 2025 IEEE 7th International Conference on Emerging Electronics (ICEE), pp. 1–4, 2025.

[9] P. Chaurasia, M. Goswami, and P. K. Misra, “An Ultra Low Power Variable Gain Amplifier Based on Negative Impedance for Low-IF Receiver Applications,” in 2025 IEEE 7th International Conference on Emerging Electronics (ICEE), pp. 1–4, 2025.

[10] U. Singh, S. Kourav, R. Ahmad, K. Kandpal, and P. K. Misra, “A Proposed Dual-Band Low-Noise Amplifier With Tunable Gain and SNDR Characteristics,” in 2025 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bengaluru, India, 2025, pp. 1–5.

[11] R. S. Siddanath, M. Gupta, R. D. Rao, S. K. Das, R. M. Hegde, P. K. Misra, M. Goswami, and K. Kandpal, “High-Precision BGR Design with Advanced Curvature Compensation & Optimized Layout in 28 nm CMOS Technology,” in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2025.

[12] S. Kourav, M. Goswami, and P. K. Misra, “A 27 mW, 3 dB NF, 3 GHz Bandwidth CMOS Ultra Wideband Power Amplifier for Short Range Communication,” in IEEE INDICON, 2024.

[13] S. Kannaujiya, K. Kandpal, and P. K. Misra, “A 16 mW 44 dB Gain Wideband Low Noise Amplifier for Ultra Wideband Applications,” in IEEE INDICON, 2024.

[14] S. K. Jha, A. Khatoon, P. Tiwari, K. Kandpal, M. Goswami, and P. K. Misra, “Low IF CMOS Receiver with 3-stage LNA for Sub-GHz Communication,” in International Symposium on Electronic System Design (ISES), 2024.

[15] A. Khatoon and P. K. Misra, “A 72 mW, 50 MHz Bandwidth Low-IF CMOS Receiver Frontend with Improved Linearity and Dynamic Range,” in International Symposium on Electronic System Design (ISES), 2024.

[16] P. Tiwari and P. K. Misra, “Fast and Energy Efficient (0.01–2.78 aJ) Logic In Memory Module using SRAM Cells,” in IEEE CONECCT, 2024.

[17] P. K. Yadav and P. K. Misra, “A Double-Resistive Feedback Active Inductor based Receiver Frontend using 40 nm CMOS Process for 28 GHz Applications,” in IEEE INDICON, 2022.

[18] J. S. Kumar, B. Kumari, P. Kumar, A. Verma, P. K. Yadav, S. Ambulker, M. Goswami, and P. K. Misra, “Design of Transceiver at 865–867 MHz Band using UMC 180 nm Technology,” in VDAT, 2020.

[19] J. K. Mishra, P. K. Misra, and M. Goswami, “Design of SRAM Cell using Voltage Lowering and Stacking Techniques for Low Power Applications,” in IEEE Asia Pacific Conference on Circuits and Systems, 2020.

[20] J. K. Mishra, P. K. Misra, and M. Goswami, “A Low Power 7T SRAM Cell using Supply Feedback Technique at 28 nm CMOS Technology,” in Seventh International Conference on Signal Processing and Integrated Networks, 2020.

[21] A. Verma, M. Goswami, and P. K. Misra, “Impact of Stages on the Performance of LNA Using RFCMOS and BiCMOS Technology for 5G Wireless Receiver Applications,” in International Conference on Microelectronics, Circuits & Systems, 2018.

[22] D. Sachan, M. Goswami, and P. K. Misra, “A Comparative Study of 5G Wireless Receiver Frontend at 28 GHz Frequency using RFCMOS and BiCMOS Technologies,” in International Conference on Microelectronics, Circuits & Systems, 2018.

[23] D. Sachan, M. Goswami, and P. K. Misra, “Analysis of Modulation Schemes for Bluetooth-LE Module for Internet-of-Things (IoT) Applications,” in IEEE International Conference on Consumer Electronics, 2018.

[24] A. Pandey, A. Verma, and P. K. Misra, “A 3.3 dB Noise Figure, 60 mW CMOS Receiver Front End for 865–867 MHz Band,” in Conference on Information and Communication Technology (CICT), 2018.

[25] P. Srivastava, P. K. Yadav, and P. K. Misra, “Design of 32-bit Asynchronous RISC CPU Using Micropipeline,” in Conference on Information and Communication Technology (CICT), 2018.

[26] R. Kumar, S. S. Yadav, A. K. Sihara, D. Sachan, and P. K. Misra, “Design of Active Inductor at 2.4 GHz Frequency using 180 nm CMOS Technology,” in UPCON, 2017, pp. 477–481.

[27] P. K. Yadav and P. K. Misra, “Power Aware Study of 32-bit 5-stage Pipeline RISC CPU using 180 nm CMOS Technology,” in IEEE INDICON, 2017.

[28] P. K. Misra and S. Qureshi, “Analog/RF Performance of NPN SiGe HBT on Thin Film SOI Over −55 to +125 °C Temperature Range,” in International Semiconductor Device Research Symposium, Dec. 2013.

[29] P. K. Misra and S. Qureshi, “Process and Device Simulations to Study the Impact of Ge Profile of 65 nm NPN SOI HBT with Buried Layer,” in IEEE INDICON, Dec. 2013.

[30] P. K. Misra and S. Qureshi, “Speed Enhancement of NPN SiGe HBT on Thin Film SOI and Thin BOX Using Substrate Bias in (0V–3V) Range,” in IEEE TENCON, Indonesia, Nov. 2011, pp. 797–801.