August 18, 2026 03:45 am
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Dr. Kavindra Kandpal

Dr. Kavindra Kandpal

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विभाग :
Department of Electronics and Communication Engineering
वर्तमान पदनाम :
Associate Professor
शैक्षणिक योग्यता:
PhD
व्यक्तिगत वेबसाइट:
https://profile.iiita.ac.in/kavindra/
मोबाइल:
+91-9569458308
ईमेल:
kavindra@iiita.ac.in
कार्यालय का पता :
Dr. Kavindra Kandpal,
Associate Professor,
Department of Electronics and Communication Engineering,
Indian Institute of Information technology, Allahabad,
CC1,2225,IIITA,Jhalwa
Prayagraj UP,211015, India. U.P. INDIA
Email: kavindra@iiita.ac.in, kavindra_ec@yahoo.com
Phone: +91532-2922437

Education

  • B. Tech. (Electronics and Telecommunication Engineering), Kumaon Engineering College Dwarahat, 2010.
  • M. Tech. (Microelectronics), Indian Institute of Information Technology Allahabad, Prayagraj, 2012.
  • Ph. D. (EEE Department), Microelectronics, Birla Institute of Technology and Science Pilani, 2018.

Professional Experience

  • Associate Professor, Electronics and Communication Engineering, IIIT Allahabad, (since Feb. 2026)
  • Assistant Professor, Electronics and Communication Engineering, IIIT Allahabad, (Dec. 2019 - Feb. 2026)
  • Assistant Professor, Electrical and Electronics Engineering Department, BITS Pilani, Pilani Campus (Jan. 2016 - Dec. 2019)
  • Lecturer, Electrical and Electronics Engineering Department, BITS Pilani, Pilani Campus (Sep. 2013 - Dec. 2015)
  • Assistant Professor, ECE Department, SIT Pithoragarh (Sep. 2012 - Aug. 2013)

Teaching

Courses Taught at IIITA (2019 onwards):

  1. Digital System Design (P.G.), 2022-2025
  2. Low Power System Design (U.G., P.G.), 2022-2025
  3. Digital IC Design (U.G.) 2023
  4. Digital System Design (U.G.), 2019-2020
  5. Modeling and Analysis of Semiconductor Devices (U.G.) 2020-2021
  6. Surface Mount Technology (U.G.), 2020-2021
  7. Fundamental of Electrical and Electronics Engineering, 2020-2021,2024-2026
  8. Hardware Design Methodology (P.G.), 2020-2021
  9. Digital System Design (P.G.), 2021-2022
  10. Analog Electronics (U.G.), 2021-2022
  11. Hardware Design Methodology (P.G.), 2021-2022

Courses Taught at BITS Pilani (2013 - 2019):

  1. Analog-Digital VLSI Design (U.G.)
  2. VLSI Design (P.G.)
  3. Analog Electronics (U.G.)
  4. VLSI Architecture (P.G.)
  5. Modeling of Field Effect Nano Devices (U.G.)
  6. Microelectronics (U.G.)
  7. Electrical Sciences (U.G.)

Sponsored Projects

  1. Device-to-Circuit Integrated Design of ZnO TFT based Pixel Circuits on Flexible Substrates
    Funding Agency: Seed Money Project, IIIT Allahabad
    Duration: 2021-2023
    Role: PI
    Approved Funds: 9.44 lakhs INR
  2. Nanometer scaled Topological Insulators for future micro and opto electronic applications
    Funding Agency: DST, SERB, Grant No. CRG/2022/000070
    Duration: 2023-2026
    Role: Co-PI
    Approved Funds: 3256264 Rs
  3. ML Enabled RISC-V based i-LORA SOC for Forest event monitoring
    Funding Agency: Chips to Startup (C2S), Ministry of Electronics & Information Technology
    Duration: 2023-2028
    Role: Co-CI
    Approved Funds: 96 lakhs INR
  4. A Unified In-Memory Computing (IMC) Radiation-Hardened Dual-Port Memory Architecture Funding Agency: Council of Science & Technology U.P., Grant No. CST/E&T/D-979
    Duration: 2026-2028
    Role: PI
    Approved Funds: 15.08 lakhs INR

Travel Grants/ Awards/ Sponsored Workshops:

1. Recipient of ANRF International Travel Scheme (ITS/2025/000326), INR 111503/- for attending AICAS 2025 held in Bordeaux, France.

2. Program Coordinator of a 6-month AICTE QIP-PG program on From Semiconductors to Chips: IC Design Fundamentals (SemChips).

Publication Details:

ORCID: https://orcid.org/0000-0002-2683-2230

Google Scholar: https://scholar.google.com/citations?user=vXYksNwAAAAJ&hl=en 

Research Interest

  1. CMOS Memory Design and IMC Architectures: CMOS/ FinFET based memory, non-volatile Memory, In-memory computing architectures, Rad-hard memory 
  2. Device Circuit Co-Design: Oxide TFTs: TCAD modeling,  SPICE integration, pixel circuits. Topological Insulator (TI) based Devices: Photodetectors, FETs and Diodes, Semiconductor applications of TI
  3. CMOS Microelectronics: Band Gap references, Analog-to-Digital Converters, High Speed comparators, Hardware Security: Physically Unclonable functions, AES, Voltage and current reference
     

  1. Track Chair, 19th IEEE Dallas Circuits and Systems conference, 2026.
  2. Organized, Self Financed,1-month duration “Summer Training Program on VLSI Design” STPVD 2020 to 2025. , ECE Department of IIIT Allahabad technically co-sponsored by IEEE UP Section/ CAS Chapter. 
  3. Organized AICTE QIP-PG Certification program on ‘From Semiconductors to Chips: IC Design Fundamentals’, SemChips at IIIT Allahabad from 1st July to 31st Dec. 2025.
  4. Delivered an expert talk on “Device Circuit co-design using Oxide TFTs” during the Faculty Development Programme on “Advanced Semiconductor Materials, Devices, Circuits, and Systems: Emerging Trends and Future Directions," scheduled from 24th July to 2nd August 2025, organized by Department of ECE, Mahindra University in association with Department of ECE, NIT Warangal (Sponsored by Ministry of Electronics and Information Technology)
  5. Dr. Kavindra Kandpal, delivered an invited lecture on a Two Day National Seminar on "Navigating VLSI: Trends, Challenges, and Opportunities - 2027 and Beyond" organised by R.M.K. COLLEGE OF ENGINEERING AND TECHNOLOGY (An Autonomous Institution) RSM Nagar, Puduvoyal-601 206, Gummidipoondi Taluk, Tiruvallur District, Tamil Nadu, India, during 24-25th July 2025 sponsored by ANRF.
  6. Delivered an expert talk on “Navigating the Path to VLSI Industry: Motivation and Challenges from a Student's Perspective” at GEHU Bhimtal on 23 April 2024. 
  7. Organizing Chair, Workshop on Recent Advancement in Photonics, IEEE WRAP 2023 technically co-sponsored by IEEE Photonics Society, Dec. 2023, IIIT Allahabad
  8. Organized AICTE QIP-PG Certification program on ‘From Semiconductors to Chips: IC Design Fundamentals’, SemChips at IIIT Allahabad from 1st July to 31st Dec. 2025.
  9. Expert Speaker, “How young professionals can become an effective leader”, IEEE BBDITM Power and Energy Society, 3rd July 2021.
  10. Resource person for the topic “Thin Film Transistors theory and modeling” in a 5 days National level, IEEE Up-section, FDP program on ‘Simulation, Modelling, and Applications of Advanced Semiconductor Devices, July 05 -09, 2021, organized by HBTU, U.P. India.
  11. Organized and served as a Session chair, 6th IEEE Symposium on Smart Electronic Systems (iSES), 14- 16 December 2020, Chennai, India.
  12. Distinguished lecture on 5th edition of Advanced Materials Science World Congress Barcelona, Spain. Delivered a talk on Oxide TFTs: Towards Transparent and Flexible Pixel Circuits for AMOLED displays at Barcelona, Spain, From 27th March-28th March 2023
  13. Session Chair, VDAT IIT Jammu (17th-19th July 2022) on Memory Design track.
  14. Served as the reviewer/ TPC member of various conferences like VLISD, VDAT, ICEE, INDICON, ISCAS and various journals like IEEE TED, TCAS, TNANO, JID, Microelectronics Journal, Scientific Report, Integration, IEEE Sensor Journal.